When Nvidia first previewed its next-generation Vera Rubin architecture nearly a year ago, the preliminary memory and interconnect numbers looked almost too aggressive to be true. Even though the industry-standard JEDEC specification for HBM4 doubled the memory bus width per stack from 1,024 bits to 2,048 bits while targeting a conservative 8.0 Gbps/pin clock rate, Nvidia projected that each 8-stack Rubin GPU would scream along at 10.75 Gbps/pin —delivering a staggering 22 TB/s of HBM4 memory bandwidth alongside 3.6 TB/s of per-GPU NVLink interconnect speed.
Now, as Q4 2026 production hardware is finally rolling off assembly lines and hyperscalers begin making the first Vera Rubin NVL72 racks available to enterprise customers, Nvidia has locked in its final shipping specifications—and physics has forced a pragmatic compromise.
According to updated architecture datasheets and product specifications, Nvidia has trimmed single-GPU Rubin HBM4 memory bandwidth by roughly 11% (from 22 TB/s down to 19.2 TB/s) and dialed back NVLink scale-up bandwidth by 17% (from 3.6 TB/s down to 3.0 TB/s) . Even more consequential for enterprise data centers buying smaller 8-GPU air- or liquid-cooled baseboards, the HGX Rubin NVL8 platform is dropping from 8 active HBM4 stacks to 7 stacks per GPU—cutting system memory capacity by 13% (from 2.3 TB to 2.0 TB) and slashing NVL8 memory bandwidth by 26% .
On the bright side, raw FP4 compute throughput (50 PFLOPS inference / 35 PFLOPS training per GPU) hit its exact target, and scale-out networking bandwidth actually increased by 12.5% (400 GB/s $\rightarrow$ 450 GB/sNVL72 racks and HGX NVL8 nodes .
Single Rubin GPU HBM4 Bandwidth (-11%): Revised from 22 TB/s (~10.75 Gbps/pin) down to 19.2 TB/s (~9.375 Gbps/pin across 8 HBM4 stacks)—still well above the baseline 8.0 Gbps/pin HBM4 spec and AMD’s rival MI455X (7.6 Gbps/pin).Single Rubin GPU NVLink Bandwidth (-17%): Scale-up NVLink interconnect dropped from 3.6 TB/s to a flat 3.0 TB/s per GPU (-600 GB/s).Scale-Out Networking Boost (+12.5%): Per-GPU scale-out networking rose from 400 GB/s to 450 GB/s , lifting full-rack Vera Rubin NVL72 bidirectional scale-out bandwidth from 28.8 TB/s to 32.4 TB/s (while NVL72 cumulative HBM4 bandwidth settled at 1,400 TB/s vs. 1,580 TB/s preliminary, and rack NVLink settled at 216 TB/s vs. 260 TB/s preliminary; total rack capacity remains 20.7 TB ).The Big Cut on HGX/DGX Rubin NVL8 (-13% RAM, -26% Bandwidth): Unlike the full 288GB GPUs in the NVL72 rack, 8-way HGX Rubin NVL8 (both x86 and Vera CPU variants) and DGX NVL8 systems now ship with 2.0 TB of total HBM4 instead of 2.3 TB (~250–252 GB per GPU using 7 of 8 HBM4 stacks ), reducing per-GPU memory bandwidth by 26% to 16.8 TB/s and trimming NVL8 training compute from 280 to 270 PFLOPS (FP4) and 140 to 130 PFLOPS (FP8).Unchanged FP4 Inference Throughput: Theoretical compute remains locked at 50 PFLOPS of FP4 inference and 35 PFLOPS of FP4 training per full Rubin GPU (400 PFLOPS FP4 inference on NVL8). Preliminary vs. Shipping Specs: Where the Bandwidth Moved
Why did Nvidia trim HBM4 pin speeds from 10.75 Gbps/pin to 9.375 Gbps/pin and disable the 8th HBM4 stack on HGX NVL8 systems? The answer comes down to manufacturing yield at massive volume .
When memory suppliers (SK Hynix, Samsung, and Micron) fabricate 2,048-bit HBM4 stacks and TSMC packages eight of those stacks onto a massive CoWoS interposer alongside the Rubin compute dies, requiring every single pin on all eight stacks to sustain 10.75 Gbps—34% above the official JEDEC HBM4 baseline—creates a brutal yield bottleneck. By relaxing the clock target to 9.375 Gbps/pin on full 8-stack GPUs (for the flagship NVL72 racks) and salvaging 7-stack Rubin packages (~250 GB capacity, 16.8 TB/s bandwidth) for the 8-GPU HGX/DGX NVL8 line, Nvidia can ship vastly more production systems in Q4 2026 and 2027 without throwing away partially yielded silicon.
Hardware Platform & Metric
Preliminary Target Spec
Final Production Shipping Spec
Net Change & Architectural Impact
Single Rubin GPU (Full) 288 GB HBM4 @ 22.0 TB/s ; 3.6 TB/s NVLink
288 GB HBM4 @ 19.2 TB/s ; 3.0 TB/s NVLink
-11% HBM4 BW , -17% NVLink , +12.5% Scale-Out (450 GB/s)
Vera Rubin NVL72 Rack 1,580 TB/s HBM4; 260 TB/s NVLink; 28.8 TB/s Net1,400 TB/s HBM4; 216 TB/s NVLink; 32.4 TB/s NetRetains full 20.7 TB capacity & 50 PFLOPS/GPU FP4 inference
HGX / DGX Rubin NVL8 (8-GPU) 2.3 TB HBM4 (288 GB/GPU, 8 stacks); ~22.7 TB/s/GPU2.0 TB HBM4 (~250 GB/GPU, 7 stacks); 16.8 TB/s/GPU -13% RAM capacity , -26% HBM4 BW , +12.5% Net (1.8 TB/s)
AMD Instinct MI455X (Rival Context) HBM4 @ ~7.6 Gbps/pin
HBM4 @ ~7.6 Gbps/pin
Rubin’s revised 9.375 Gbps/pin still leads MI455X pin rate by +23%
Single Rubin GPU (Full)
Preliminary Target Spec 288 GB HBM4 @ 22.0 TB/s ; 3.6 TB/s NVLink
Final Production Shipping Spec 288 GB HBM4 @ 19.2 TB/s ; 3.0 TB/s NVLink
Net Change & Architectural Impact -11% HBM4 BW , -17% NVLink , +12.5% Scale-Out (450 GB/s)
Vera Rubin NVL72 Rack
Preliminary Target Spec 1,580 TB/s HBM4; 260 TB/s NVLink; 28.8 TB/s Net
Final Production Shipping Spec 1,400 TB/s HBM4; 216 TB/s NVLink; 32.4 TB/s Net
Net Change & Architectural Impact Retains full 20.7 TB capacity & 50 PFLOPS/GPU FP4 inference
HGX / DGX Rubin NVL8 (8-GPU)
Preliminary Target Spec 2.3 TB HBM4 (288 GB/GPU, 8 stacks); ~22.7 TB/s/GPU
Final Production Shipping Spec 2.0 TB HBM4 (~250 GB/GPU, 7 stacks); 16.8 TB/s/GPU
Net Change & Architectural Impact -13% RAM capacity , -26% HBM4 BW , +12.5% Net (1.8 TB/s)
AMD Instinct MI455X (Rival Context)
Preliminary Target Spec HBM4 @ ~7.6 Gbps/pin
Final Production Shipping Spec HBM4 @ ~7.6 Gbps/pin
Net Change & Architectural Impact Rubin’s revised 9.375 Gbps/pin still leads MI455X pin rate by +23%
Look closely at the third row of that table. If your infrastructure team is ordering full rack-scale Vera Rubin NVL72 systems, your total HBM4 capacity (20.7 TB) and FP4 compute are 100% intact, and the 11% dip in memory bandwidth is partially offset by a 12.5% boost in scale-out networking (32.4 TB/s).
However, if your team is ordering 8-GPU HGX Rubin NVL8 or DGX Rubin NVL8 server nodes, you are getting a fundamentally binned GPU tier: 300 GB less HBM4 capacity per server (2.0 TB vs 2.3 TB) and 26% less memory bandwidth (16.8 TB/s per GPU) .
Practical Impact on LLM Inference, MoE Routing, and Cluster Sizing
Not every AI workload cares equally about an 11% to 26% drop in HBM4 bandwidth or a 17% reduction in NVLink speed:
Prefill & Compute-Bound Workloads (Minimal Impact): Processing long input prompts (prefill) or running dense matrix multiplications at FP4 precision is compute-bound. Because Rubin hit its full 50 PFLOPS FP4 inference clock target, prefill latency will match initial projections.Autoregressive Token Decoding (Direct Impact): Generating output tokens one-by-one is almost purely memory-bandwidth bound , because the GPU must stream model weights from HBM4 into SRAM for every generated token. An 11% reduction in HBM4 bandwidth on NVL72 (and a 26% reduction on NVL8) translates nearly 1:1 into lower maximum tokens-per-second per user at low batch sizes.Trillion-Parameter MoE All-to-All Communication: Mixture-of-Experts (MoE) models rely heavily on NVLink for intra-rack expert parallelism (-17% bandwidth) and scale-out networking for cross-rack communication (+12.5% bandwidth).
The 4-Step Enterprise Implementation Playbook
Re-Verify KV-Cache Headroom on 8-GPU HGX/DGX Rubin NVL8 Orders: If your capacity planners sized 2027 HGX Rubin NVL8 servers assuming 2.3 TB (2,304 GB) of HBM4 to hold a massive trillion-parameter model plus long-context KV caches, update your spreadsheets to 2.0 TB (~250 GB/GPU)Discount Single-Stream Decode Token/s Estimates by 11% (NVL72) and 26% (NVL8): Update your internal TCO models comparing Blackwell Ultra against Vera Rubin. For memory-bound autoregressive token generation, use 19.2 TB/s (NVL72) and 16.8 TB/s (NVL8) rather than the preliminary 22 TB/s marketing numbers when calculating cost per million output tokens.Shift Multi-Rack Training Topologies to Exploit the +12.5% Scale-Out Boost: Because Nvidia increased scale-out networking from 400 GB/s to 450 GB/s per GPU32.4 TB/s per NVL72 rack, 1.8 TB/s per NVL8 node), configure distributed training jobs (such as PyTorchtensor/pipeline parallelism) to lean more heavily on inter-node scale-out fabric rather than assuming 3.6 TB/s intra-node NVLink.Benchmark Price-Performance Against Blackwell Ultra and AMD MI455X: Even at 9.375 Gbps/pin, full Rubin GPUs still outpace AMD’s MI455X (7.6 Gbps/pin) on per-pin HBM4 speed. However, for 8-GPU air-cooled enterprise deployments where Rubin NVL8 is binned down to 7 stacks (16.8 TB/s), demand a price-per-node discount from your OEM server vendor or cross-shop against discounted Blackwell Ultra HGX B300 inventory.
Next Steps
